The present invention is related generally to integrated circuit testers, and more specifically to testing AC functional characteristics, particularly propagation delay times, of high speed integrated circuit devices.
A circuit tester applies digital signal patterns called test vectors to the electrical connections (pads or pins) of a device under test (xe2x80x9cDUTxe2x80x9d). A schematic diagram of an available tester is provided in FIG. 1. Tester 1 comprises a central processing unit (xe2x80x9cCPUxe2x80x9d) 10 connected to external elements such as terminal 11, printer 12, and port 13 for establishing a link with other apparatus such as a communication link with a host computer. CPU 10 is also connected to bus 14 for transmitting and receiving data to and from various tester elements.
The DUT is connected to the tester through a contactor socket (not shown) and a load board 15. The input/output connections of the socket normally correspond to the pins of the device to be tested, each pin being connected to a specific card referred to as an electronic pin 16 (only one of which is shown in FIG. 1) which constitute in plurality a set of boards, arranged generally as a ring. Pins 16 comprise a bidirectional link with a test vector memory 17 and a specific link with a terminal of load board 15. Pins 16 also provide access to common circuits for providing reference voltages 19 and time delays 19xe2x80x2 via general bus 14. Each electronic pin 16 comprises amplitude and time shaping circuits for adjusting the signals received from memory 17 to match the references provided by circuits 19 and 19xe2x80x2. Load board 15 may comprise buffer impedances and read relays for connecting the integrated circuit pins of the DUT either to an electronic pin 16 or to central measuring unit (CMU) 18 which applies and measures currents and voltages.
As integrated circuit devices become faster, the propagation delay (TPD) through a device (e.g., from an input pin to an output pin) must be more precisely measured to ensure accurate verification of device operation. Referring to FIG. 2, TPD can be defined as the length of time that passes from point B in the timing diagram for signal DUTIN, to point C in the timing diagram for signal DUTOUT. Since the specifications for an especially fast device might call for a very small TPD (e.g., 5 nanoseconds), and the propagation delay of the path through the testing apparatus itself (tester delay from point A to point B in FIG. 2) may be comparable to the TPD of the device (e.g., 8 nanoseconds), the tester delay must be accurately measured and accounted for to properly measure TPD at a fine scale. Too much error in tester propagation delay measurement leads to unreliable TPD measurement, thereby potentially decreasing the number of verified-TPD high-speed devices yielded after testing. Also, it is critical to place points B and C at the appropriate point in a rising or falling skew line, to ensure accurate pass/fail measurements during testing.
Referring next to FIG. 3, it is presently known to use comparator circuit 20 to measure tester propagation delay through a tester signal path (between the pin electronics within the test head (not shown), through connections 44 to the load board 15, contactor 40, and DUT 42) using a technique commonly referred to as Time Domain Reflectometry (TDR). In a TDR measurement, a step waveform signal is sent through a test channel from driver 30 in the test head to a high impedance load (e.g., the open socket) in load board 15. The signal reflects from the open socket and returns to its source. The elapsed time is measured when the reflected waveform returns to its source, and the tester path delay is half the measured elapsed time.
While TDR can provide valuable delay information, its accuracy is limited by the specifications of comparator circuit 20, which is illustrated in detail in FIG. 4. In comparator circuit 20, digital to analog converter (DAC) 24 provides a reference voltage VOL for comparison to driver-supplied input signal VOUT by comparator 26. Driver-supplied input signal VOUT is provided by driver 30 in FIG. 3. The output of comparator 26 is then forwarded to logic comparator 22. Each time logic comparator 22 receives an activation signal from strobe 28, logic comparator 22 provides either a logic high or logic low signal depending upon the output of comparator 26. Strobe 28 is activated at a precisely known time, thereby accurately indicating the logic level of the signal forwarded by comparator 26.
There are two variables that determine the accuracy of comparator circuit 20: the step size (also known as comparator voltage resolution) of the test stimulus digital signal received by DAC 24, and the precise timing of the strobe signal received from strobe 28. Strobe resolution is often the limiting factor in testing error. While strobe resolution is limited to about a 0.1 nanosecond step (100 picoseconds, two percent of a 5 nanosecond delay), presently available reference voltage resolution (generated by DAC 24 and forwarded to comparator 26 in FIG. 4) is generally about a 2.5 millivolt step for a 0 to 3 volt signal (only about 0.08 percent error from coarse resolution). In device lots having a TPD standard deviation of 100 picoseconds or less, the error created by the coarse resolution of strobe signals is therefore significant and can lead to costly reductions in yield. Therefore, there is a need in the integrated circuit testing field for a method of increasing the effective resolution of test strobe signals.
A method and system are provided for increasing the accuracy of AC parametric testing. The invention provides for the derivation of highly accurate response characteristics through linear interpolation and extrapolation. The invention further allows for the utilization of test signals having almost any discrete time value and voltage magnitude by modifying the input signals and output testing points according to extrapolated voltage and timing values, thereby substantially reducing measurement error, increasing test efficacy, and boosting high-speed device yield.
The invention provides a method of precisely estimating tester delays (signal propagation delay time in an integrated circuit testing apparatus), wherein a plurality of tester delay measurements are taken and additional delays are estimated by linearly interpolating the measured delays.
The invention also provides a method of precisely estimating propagation delays through a device via linear extrapolation. A desired test point (desired output voltage at a given time) is established. Using a sample device, output voltage measurements are taken at a plurality of strobe times. Using these voltage measurements, a slope is established on a time vs. voltage plot for the sample device. This slope is then applied to a line through the desired test point. Where a desired test point falls between strobe times on a tester, linear extrapolation from the desired test point is used to calculate what voltages must be tested for at the two bracketing strobe times in order to guarantee the desired performance at the desired test point. One or more devices are then tested for the calculated voltages at the corresponding bracketing strobe times. If a device passes both tests, it may be assumed (to a desired level of accuracy) that the device would pass the test at the desired test point, if it were possible to make such a test.
Two test points bracketing the desired test point may be used, as previously described. This method provides a relatively high degree of accuracy, even where a DUT has a response curve with a slightly different slope than the sample device. In an embodiment requiring less accuracy only one test point is used. In another embodiment, two test points not bracketing the desired test point are used.